A. Field of the Invention
The present invention relates to a dynamic type semiconductor memory apparatus, and more particularly, to a dynamic type semiconductor memory apparatus that performs a continuous column access operation at a higher speed than a conventional memory apparatus while restraining a chip size increase to a minimum.
B. Background of the Invention
Recently, it has been required to perform operations of a dynamic type semiconductor memory (DRAM) apparatus at a higher speed. To meet the need of a higher accessing speed of a DRAM, it has conventionally been proposed to perform a continuous access of a plurality of memory cells that are connected to one word line by changing only a column address. This method is referred to as a continuous column access operation.
In spite of the fact that the continuous column access operation is beneficial to a transfer of a large volume of data at a high speed, it is difficult to control a timing for performing a data reading operation at the high speed, immediately after a data writing operation has been completed. Since a data read buffer (DRB) and a data write buffer (DWB) are disposed in an external area of a memory cell alley, a wiring capacity of each data line connecting a bit line to both the DRB and DWB becomes much bigger than the capacity of the bit line. Consequently, it takes a longer time in order to charge the data line previous to transmit the data across the data line, which limits the speed of the memory device. This is a serious drawback for the conventional memory devices for achieving the continuous column access operation at a higher speed.
In particular, it takes a long time to pre-charge the data line for a data write operation because the data line is driven by the DWB that has a larger driving function for reversing a bit line sense amplifier through a transfer gate. Consequently, operation timings of the data lines for performing a data write operation into a memory cell through the data line and for performing a data read operation from another memory cell through the same data line become slow and difficult to control. Such a timing control of the data line becomes the most severe problem for the conventional memory devices regarding the increase in the speed transfer of data. To solve the problem of the timing control of the data line, Japanese Patent Application Publication 7-282583 (herein '583) has proposed one method for connecting two—accessing circuits and one bit line.
However, the method of '583 needs to provide two main amplifiers for each of the memory cell alleys. The main amplifier corresponding to the above-explained DRB and DWB requires a large layout area. Accordingly, the method of '583 has an inevitable drawback of a large increase of the chip size. Since a recent development of the dynamic type semiconductor memory apparatus mainly introduces a hierarchy configuration for the data lines in order to increase a capacity of the DRAM, the layout areas for the DRB and DWB are extremely increased so as to drive a master data line having a large wiring capacity. However, the industry requires memory devices having a small area, which is a problem for the above discussed memory device of the '583 reference.
Further, the method disclosed in the '583 reference cannot achieve an actual high speed operation of data access for a DRAM that has a high speed serial input/output function. To increase a bandwidth for a data transfer in such a DRAM having a high speed function, the DRAM needs to simultaneously access the data having a data size from 128 bit to 1024 bit in the memory cell unit and also needs to transmit and receive the data at a high speed to and from an external unit through a parallel/serial conversion circuit. Thus, the DRAM needs to provide the same numbers of DRB and DWB for the respective bits in order to simultaneously access the same memory cell unit. For example, the DRAM needs to increase the numbers of the DRB and DWB to at least twice the numbers of the DRB and DWB of a conventional memory device. Consequently, the conventional devices cannot achieve a high speed operation without considerably increasing the chip size.
As mentioned above, the conventional dynamic type semiconductor memory apparatus has problems in performing the high speed of continuous column access operation without increasing the chip size. Actually, such an increase of the chip size is not permissible from an industrial aspect because of the required cost performance relation for the recent DRAM.